1. Field of the Invention
This invention relates to a phase compensation method for regenerator equipment, and particularly, to a phase compensation method for regenerator equipment to compensate the phase of regenerated data in optical regenerator equipment for dropping and inserting monitor station data.
2. Description of the Prior Art
Data links carry out communications between line terminating equipment consisting of data processing equipment and terminal equipment.
Because optical data links are composed of optical fibers, they are virtually free from electrical interference and thus have realized high quality data transmission.
Also because these optical data links have low signal loss, they have the capability to carry out long distance transmissions of several kilometers. If long distance communication is to be carried out between line terminating equipment (for example intercity or intercontinental communications), using optical regenerators as data links makes it possible to lengthen communication range.
FIG. 10 shows the layout of an optical regenerator system which uses optical data links to connect a plurality of line terminating equipment. As the figure shows, 511 and 513 are line terminating equipment, 515 is an optical regenerator equipment, 517 is an optical data link, and 521, 523 and 525 are the monitor control sections. Line terminating equipment 511 and line terminating equipment 513 are connected to optical data link 517 using several units of optical regenerator equipment 515. Also monitor control section 521 monitors line terminating equipment 511 for trouble and monitor control section 521 does the same for line terminating equipment 513. In the same way each optical regenerator equipment 515 of the optical data link 517 are each checked by a plurality of monitor control sections 525 for possible trouble.
FIG. 11 shows the layout of each optical regenerator unit 515. In the drawing, 611 is an optical/electrical convertor, 613, 615, 623, 625, 635 and 641 are level convertor circuits, 621 is an electrical/optical convertor, 631 is a multiplexer, 633 is an ECL-LSI, and 637, 639 are OR-NOR gates. Each optical regenerator equipment 515 has an optical/electrical convertor 611, an electrical/optical convertor 621, and a multiplexer 631.
The optical/electrical convertor 611 changes the optical signal that was input through the optical data link 517 into an electrical signal (digital signal) and also extracts the clock signal. The converted electrical signal (serial data) is changed into parallel data and output from the optical/electrical convertor 611. The development of this technical method makes it possible to convert various data (such as processing by the multiplexer 631 to be covered later and recovery of weak signals) at high speed from optical signals to electrical ones.
Because the input and output of data to and from the optical regenerator equipment is at an extremely high speed and the clock signal must be at least twice that speed, it is necessary to change the input level of the clock in order to protect against reflection occurring. Level convertor circuits 613 and 615 carry out this change in signal. Thus the ECL level clock is converted to 1 V, -1 V level clocks.
After electrical/optical convertor 621 has changed the inputted electrical signal (parallel data) along with the synchronized clock signal from the optical/electrical convertor 611 into serial data, the (now) optical signal is sent to optical data link 517. Because data inside the electrical/optical convertor 621 is handled at ECL levels, the data input to the clock is changed to ECL levels by level convertor circuit 625. A clock is also input from multiplexer 631 and changed to ECL levels by level convertor circuit 623 but this clock is to be used as a spare.
A portion of the parallel data output from optical/ electrical convertor 611 and the clock multiplexer signal are entered into electrical/optical convertor 621, by using multiplexer 631. Then, the remainder of the parallel data output from optical/electrical convertor 611 and the clock signal are directly entered into electrical/optical convertor 621.
The multiplexer 631 includes ECL-LSI 633 which carries out multiplexing and demultiplexing of data, level convertor circuit 635 which changes the signal to ECL levels, OR-NOR gates 637, 639 which carry out signal separation of the ECL level clock and level convertor circuit 641 which changes the ECL clock level to 0 V, -1 V levels.
After the clock signal input to the multiplexer 631 is changed to ECL level by the level convertor circuit 635, it is input to ECL-LSI 631 using the OR-NOR gates 637 and 639. By means of ECL-LSI 633, the clock signal isolated out by OR-NOR gate 637 is used for data separation and the clock data isolated by OR-NOR gate 639 is for data multiplexing. ECL-LSI 633 is connected to monitor control section 525 by means of data input/output controller CMOS-LSI (not shown). At the designated position of the synchronized frame (hereinafter called the service channel), data results from monitor control section 525 are inserted and data designated by the monitor section are dropped from the service channel and sent to monitor control section 525.
Generally, the multiplexer 631 is a semiconductor device, and the phase of the data output from the multiplexer varies with the temperature and the voltage. The source of this variation is in the total sum of the delay time by ECL-LSI itself and the delay variation by the level convertor circuit 635 and the OR-NOR gates 637 and 639. FIGS. 12(a) and 12(b) show the switching characteristics of the OR-NOR gates 637, 639 made of Fujitsu-made semiconductor device ECL-IC (model No. MB810A). FIG. 12 (a) shows the temperature dependence of the propagation delay time. FIG. 12 (b) shows the output rise and fall time characteristics as related to temperatures. As the figure shows, when the temperature increases the propagation delay times become longer and the rise and fall times also increase. Level convertor circuit 635 and ECL-LSI 633 show the same trend. There is also a variation in the phase in proportion to a change in voltage.
Factors like those mentioned above cause a difference to occur in the phases between data supplied using multiplexer 631, and data from the combined data of the clock and optical/electrical convertor 611. However the electrical/ optical convertor 621 operates as synchronized with the clock supplied directly from optical/electrical convertor 611, so that the input phase margin of the data input from multiplexer 631 must be maintained.
FIG. 13 shows the state of overall output (for data and clock) phase change of multiplexer 631 due to temperature and voltage. The figure shows respectively, "Power Variations" which are voltage variations, "Delay Time" which is a phase variation, and "temperature variation" which is an operating temperature or ambient temperature variation. As FIG. 13 shows, along with a phase that gets more delayed as the temperature rises, that a higher voltage advances the phase.
FIGS. 14(a) and 14(b) show outlines of the input phase margin of electrical/optical convertor 621. According to the figure, the "Input Phase Margin" is the input phase data tolerance range of electrical/optical convertor 621. If this input phase margin is exceeded a bit data error is generated. Also the data phase change "Delay Time" is shown for data fed from the other unit when the clock fed from either multiplexer 631 or optical electrical convertor 611 is used as a standard.
FIG. 14 (a) shows the input data margin regarding data supplied from the multiplexer when the electrical/optical convertor 621 operates upon being synchronized by the clock fed from optical electrical convertor 611. Accordingly, problems have occurred with the input phase margin disappearing as the temperature falls or the voltage rises.
In FIG. 14 (b), the input phase margin of data directly fed from optical electrical convertor 611 is shown when electrical/optical convertor 621 operates upon being supplied a synchronized signal from the spare clock fed by multiplexer 631. Accordingly, problems have occurred with the input phase margin disappearing completely with a rise in temperature or a drop in voltage.
Because noise-generated data errors occur easily when the phase margin disappears as described, there have been problems with drops in communication efficiency.